809 search results - page 79 / 162 » Variations in Cache Behavior |
ISCA
2002
IEEE
15 years 4 months ago
2002
IEEE
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
106
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PDP
2010
IEEE
15 years 4 months ago
2010
IEEE
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
RTSS
1999
IEEE
15 years 4 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
113
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ICS
2000
Tsinghua U.
15 years 3 months ago
2000
Tsinghua U.
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
SODA
2003
ACM
15 years 1 months ago
2003
ACM
We tackle the problem of online paging on two level memories with arbitrary associativity (including victim caches, skewed caches etc.). We show that some important classes of pag...