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» Vdd programmability to reduce FPGA interconnect power
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DAC
2005
ACM
14 years 11 months ago
Exploring technology alternatives for nano-scale FPGA interconnects
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane I...
FTEDA
2007
156views more  FTEDA 2007»
14 years 9 months ago
FPGA Architecture: Survey and Challenges
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...
Ian Kuon, Russell Tessier, Jonathan Rose
FPL
2004
Springer
93views Hardware» more  FPL 2004»
15 years 3 months ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
15 years 3 months ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
TVLSI
2010
14 years 4 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan