Sciweavers

266 search results - page 13 / 54
» Vector instruction set support for conditional operations
Sort
View
DAGSTUHL
2008
15 years 18 days ago
Interval Arithmetic Using SSE-2
ABSTRACT. We present an implementation of double precision interval arithmetic using the single-instruction-multiple-data SSE-2 instruction and register set extensions. The impleme...
Branimir Lambov
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 5 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
MICRO
2003
IEEE
155views Hardware» more  MICRO 2003»
15 years 4 months ago
Comparing Program Phase Detection Techniques
Detecting program phase changes accurately is an important aspect of dynamically adaptable systems. Three dynamic program phase detection techniques are compared – using instruc...
Ashutosh S. Dhodapkar, James E. Smith
EUROSYS
2011
ACM
14 years 2 months ago
Symbolic crosschecking of floating-point and SIMD code
We present an effective technique for crosschecking an IEEE 754 floating-point program and its SIMD-vectorized version, implemented in KLEE-FP, an extension to the KLEE symbolic ...
Peter Collingbourne, Cristian Cadar, Paul H. J. Ke...
SOSP
2001
ACM
15 years 8 months ago
SEDA: An Architecture for Well-Conditioned, Scalable Internet Services
We propose a new design for highly concurrent Internet services, which we call the staged event-driven architecture (SEDA). SEDA is intended to support massive concurrency demands...
Matt Welsh, David E. Culler, Eric A. Brewer