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» Vector instruction set support for conditional operations
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ARCS
2010
Springer
15 years 5 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
IEEEPACT
2002
IEEE
15 years 4 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
IFIP
2010
Springer
14 years 6 months ago
A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
Abstract. In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, ne the native speed of a...
Markus Becker, Henning Zabel, Wolfgang Müller...
AAAI
2007
15 years 1 months ago
Representing and Reasoning about Commitments in Business Processes
A variety of business relationships in open settings can be understood in terms of the creation and manipulation of commitments among the participants. These include B2C and B2B c...
Nirmit Desai, Amit K. Chopra, Munindar P. Singh
CCR
2002
97views more  CCR 2002»
14 years 11 months ago
Multi-modal network protocols
Most network protocols are uni-modal: they employ a single set of algorithms that allows them to cope well only within a narrow range of operating conditions. This rigid design re...
Rajesh Krishna Balan, Aditya Akella, Srinivasan Se...