Sciweavers

266 search results - page 4 / 54
» Vector instruction set support for conditional operations
Sort
View
IPPS
2006
IEEE
15 years 5 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 3 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
DAC
1997
ACM
15 years 3 months ago
ISDL: An Instruction Set Description Language for Retargetability
Abstract—We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features ...
George Hadjiyiannis, Silvina Hanono, Srinivas Deva...
CC
2008
Springer
111views System Software» more  CC 2008»
15 years 1 months ago
A System for Generating Static Analyzers for Machine Instructions
This paper describes the design and implementation of a language for specifying the semantics of an instruction set, along with a run-time system to support the static analysis of ...
Junghee Lim, Thomas W. Reps
ASAP
2005
IEEE
93views Hardware» more  ASAP 2005»
15 years 1 months ago
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael ...