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» Verification Programs for Abduction
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EMSOFT
2004
Springer
15 years 8 months ago
Separation of concerns: overhead in modeling and efficient simulation techniques
Separating the description of important aspects of a design such as behavior and architecture, or computation and communication, may yield significant advantages in design time as...
Guang Yang 0004, Alberto L. Sangiovanni-Vincentell...
ARTS
1997
Springer
15 years 8 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
SPIN
2000
Springer
15 years 8 months ago
The Temporal Rover and the ATG Rover
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
Doron Drusinsky
ACMSE
2008
ACM
15 years 6 months ago
A self-testing autonomic job scheduler
Although researchers have been exchanging ideas on the design and development of autonomic systems, there has been little emphasis on validation. In an effort to stimulate interes...
Alain E. Ramirez, Barbara Quinones-Morales, Tariq ...
AMAST
2008
Springer
15 years 6 months ago
Towards an Efficient Implementation of Tree Automata Completion
Term Rewriting Systems (TRSs) are now commonly used as a modeling language for applications. In those rewriting based models, reachability analysis, i.e. proving or disproving that...
Emilie Balland, Yohan Boichut, Thomas Genet, Pierr...