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» Verification Under Increasing Dimensionality
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ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
15 years 4 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
IEEECIT
2005
IEEE
15 years 5 months ago
Case Study: Distance-Based Image Retrieval in the MoBIoS DBMS
Similarity search leveraging distance-based index structures is increasingly being used for complex data types. It has been shown that for high dimensional uniform vectors with si...
Rui Mao, Wenguo Liu, Daniel P. Miranker, Qasim Iqb...
DAC
2007
ACM
16 years 20 days ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
ICPR
2006
IEEE
16 years 23 days ago
New Experiments on ICP-Based 3D Face Recognition and Authentication
In this paper, we discuss new experiments on face recognition and authentication based on dimensional surface matching. While most of existing methods use facial intensity images,...
Boulbaba Ben Amor, Liming Chen, Mohsen Ardabilian
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
15 years 8 months ago
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
Lintao Zhang, Sharad Malik