714 search results - page 97 / 143 » Verification and Compliance Testing |
105
Voted
EDCC
2005
Springer
15 years 6 months ago
2005
Springer
Fault links represent relationships between the types of mistakes made and the type of module being developed or modified. The existence of such fault links can be used to guide co...
ASYNC
2002
IEEE
15 years 5 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
101
Voted
DAC
1990
ACM
15 years 4 months ago
1990
ACM
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulat...
99
Voted
ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
- In this paper we showed the signal degradation parts in High-speed channel of FB-DiMM system. And we also showed possible countermeasure. For the verification propose and also fo...
CAISE
2006
Springer
15 years 4 months ago
2006
Springer
Static function hierarchies and models of the dynamic behaviour are typically used in e-commerce systems. Issues to be verifies are the completeness and correctness of the static f...