1663 search results - page 20 / 333 » Verification and validation of simulation models |
ICSE
2008
IEEE-ACM
15 years 10 months ago
2008
IEEE-ACM
Nowadays, large-scale industrial software systems may involve hundreds of developers working on hundreds of different but related models representing parts of the same system spec...
WSC
2007
14 years 12 months ago
2007
The TCP models in ns-2 have been validated and are widely used in network research. They are however not aimed at producing results consistent with a TCP implementation, they are ...
CODES
2008
IEEE
14 years 11 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
77
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...