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» Verification and validation of simulation models
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SCESM
2006
ACM
262views Algorithms» more  SCESM 2006»
15 years 5 months ago
Scenario-driven modeling and validation of requirements models
Requirements models for large systems typically cannot be developed in a single step, but evolve in a sequence of iterations. We have developed such an iterative modeling process ...
Christian Seybold, Silvio Meier, Martin Glinz
ATVA
2007
Springer
112views Hardware» more  ATVA 2007»
15 years 6 months ago
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
Scott Little, David Walter, Kevin Jones, Chris J. ...
ICST
2009
IEEE
14 years 9 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...
FDL
2006
IEEE
15 years 5 months ago
Randomized Simulation of Hybrid Systems For Circuit Validation
Abstract. The paper proposes a simulation-based method for validating analog and mixed-signal circuits, using the hybrid systems methodology. This method builds upon RRT (Rapidly-e...
Thao Dang, Tarik Nahhal
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
16 years 5 days ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...