1663 search results - page 26 / 333 » Verification and validation of simulation models |
DKE
2008
14 years 9 months ago
2008
Knowledge validation, as part of knowledge base verification and validation is a critical process in knowledge engineering. The ultimate goal of this process is to make the knowle...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
The VOVHDL language was defined as a verification oriented VHDL
ATVA
2009
Springer
15 years 1 months ago
2009
Springer
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
ICCS
2007
Springer
15 years 3 months ago
2007
Springer
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
79
Voted
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...