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» Verification and validation of simulation models
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HVC
2007
Springer
153views Hardware» more  HVC 2007»
15 years 1 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul
CORR
2008
Springer
179views Education» more  CORR 2008»
14 years 9 months ago
Practical Automated Partial Verification of Multi-Paradigm Real-Time Models
This article introduces a fully automated verification technique that permits to analyze real-time systems described using a continuous notion of time and a mixture of operational...
Carlo A. Furia, Matteo Pradella, Matteo Rossi
SIGSOFT
2007
ACM
15 years 10 months ago
State space exploration using feedback constraint generation and Monte-Carlo sampling
The systematic exploration of the space of all the behaviours of a software system forms the basis of numerous approaches to verification. However, existing approaches face many c...
Sriram Sankaranarayanan, Richard M. Chang, Guofei ...
ISSS
2002
IEEE
144views Hardware» more  ISSS 2002»
15 years 2 months ago
A Visual Approach to Validating System Level Designs
This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual speciï¬...
Jürgen Ruf, Thomas Kropf, Jochen Klose
IWUC
2004
14 years 11 months ago
On Uncertainty in Context-Aware Computing: Appealing to High-Level and Same-Level Context for Low-Level Context Verification
There is an inherent chasm between the real-world and the world that can be perceived by computer systems, yielding uncertainty and ambiguity in system perceived context, with cons...
Amir Padovitz, Seng Wai Loke, Arkady B. Zaslavsky