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» Verification and validation of simulation models
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TON
2010
93views more  TON 2010»
14 years 4 months ago
On the Validity of IEEE 802.11 MAC Modeling Hypotheses
We identify common hypotheses on which a large number of distinct mathematical models of WLANs employing IEEE 802.11 are founded. Using data from an experimental test bed and packe...
K. D. Huang, Ken R. Duffy, David Malone
UML
2004
Springer
15 years 3 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
CORR
2004
Springer
120views Education» more  CORR 2004»
14 years 9 months ago
Validating a Web Service Security Abstraction by Typing
Abstraction by Typing Andrew D. Gordon Microsoft Research Riccardo Pucella Cornell University An XML web service is, to a first approximation, an RPC service in which requests and...
Andrew D. Gordon, Riccardo Pucella
DATE
2008
IEEE
167views Hardware» more  DATE 2008»
15 years 4 months ago
Accuracy-Adaptive Simulation of Transaction Level Models
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
Martin Radetzki, Rauf Salimi Khaligh
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 3 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski