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» Verification and validation of simulation models
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ICCAD
1996
IEEE
144views Hardware» more  ICCAD 1996»
15 years 1 months ago
Validation coverage analysis for complex digital designs
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Richard C. Ho, Mark Horowitz
INFSOF
2006
158views more  INFSOF 2006»
14 years 9 months ago
DEVSpecL: DEVS specification language for modeling, simulation and analysis of discrete event systems
Discrete EVent Systems Specification (DEVS) formalism supports specification of discrete event models in a hierarchical modular manner. This paper proposes a DEVS modeling languag...
Ki Jung Hong, Tag Gon Kim
TVLSI
2008
152views more  TVLSI 2008»
14 years 9 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
WSC
1994
14 years 11 months ago
Downtime data - its collection, analysis, and importance
Until the day when plant production personnel and equipment have no downtime, proper collection and analysis of downtime data will be essential to the development of valid, credib...
Edward J. Williams
FUIN
2008
88views more  FUIN 2008»
14 years 9 months ago
Validating Behavioral Component Interfaces in Rewriting Logic
Many distributed applications can be understood in terms of components interacting in an open environment such as the Internet. Open environments are subject to change in unpredic...
Einar Broch Johnsen, Olaf Owe, Arild B. Torjusen