1663 search results - page 60 / 333 » Verification and validation of simulation models |
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
CORR
2008
Springer
14 years 9 months ago
2008
Springer
Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing t...
DAC
1999
ACM
15 years 2 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
MASCOTS
2004
14 years 11 months ago
2004
In the ever increasing world of distributed systems, different middleware implementations can be compared qualitatively or quantitatively. Existing evaluation techniques are often...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...