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» Verification and validation of simulation models
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DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 1 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
COMPSAC
2000
IEEE
15 years 2 months ago
Automating Scenario-Driven Structured Requirements Engineering
Scenario analysis is a vehicle of separating concerns in the elicitation of users' requirements. It is also a means of requirements validation and verification. In the practi...
Hong Zhu, Lingzi Jin
ASPLOS
2000
ACM
15 years 2 months ago
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the syst...
Jeff Gibson, Robert Kunz, David Ofelt, Mark Heinri...
VVEIS
2007
14 years 11 months ago
Transformation of BPMN Models for Behaviour Analysis
Abstract. In industry, many business processes are modelled and stored in Enterprise Information Systems (EIS). Tools supporting the verification and validation of business process...
Ivo Raedts, Marija Petkovic, Yaroslav S. Usenko, J...
VL
2005
IEEE
126views Visual Languages» more  VL 2005»
15 years 3 months ago
Animated Simulation of Integrated UML Behavioral Models Based on Graph Transformation
This paper shows how integrated UML models combining class, object, use-case, collaboration and state diagrams can be animated in a domain-specific layout. The presented approach...
Claudia Ermel, Karsten Hölscher, Sabine Kuske...