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» Verification and validation of simulation models
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DAC
2004
ACM
15 years 10 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
DAC
2003
ACM
15 years 3 months ago
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
ICSE
2008
IEEE-ACM
15 years 10 months ago
A verification system for timed interval calculus
Timed Interval Calculus (TIC) is a highly expressive set-based notation for specifying and reasoning about embedded real-time systems. However, it lacks mechanical proving support...
Chunqing Chen, Jin Song Dong, Jun Sun 0001
FMICS
2006
Springer
15 years 1 months ago
SAT-Based Verification of LTL Formulas
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
Wenhui Zhang
ECRTS
1998
IEEE
15 years 2 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken