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UML
2004
Springer
15 years 6 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
KBSE
2003
IEEE
15 years 6 months ago
Semi-Automatic Fault Localization and Behavior Verification for Physical System Simulation Models
Mathematical modeling and simulation of complex physical systems are emerging as key technologies in engineering. Modern approaches to physical system simulation allow users to sp...
Peter Bunus, Peter Fritzson
DSD
2002
IEEE
102views Hardware» more  DSD 2002»
15 years 5 months ago
Formal Verification of a DSP Chip Using an Iterative Approach
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
Ali Habibi, Sofiène Tahar, Adel Ghazel
DATE
1998
IEEE
93views Hardware» more  DATE 1998»
15 years 5 months ago
Verification by Simulation Comparison using Interface Synthesis
One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel
DBPL
1997
Springer
133views Database» more  DBPL 1997»
15 years 4 months ago
Automatic Verification of Transactions on an Object-Oriented Database
Abstract. In the context of the object-oriented data model, a compiletime approach is given that provides for a significant reduction of the amount of run-time transaction overhead...
David Spelt, Herman Balsters