1914 search results - page 127 / 383 » Verification by Abstract Interpretation |
120
Voted
ICCD
2004
IEEE
15 years 9 months ago
2004
IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
ICCAD
2006
IEEE
15 years 9 months ago
2006
IEEE
– Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology...
87
Voted
ASYNC
1999
IEEE
15 years 5 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
107
Voted
CONCUR
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. We study the decidability and complexity of verification problems for timed automata over time intervals of fixed, bounded length. One of our main results is that time-bo...
103
Voted
FMCAD
2007
Springer
15 years 4 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...