5525 search results - page 13 / 1105 » Verification of Model Transformations |
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
SAC
2010
ACM
14 years 9 months ago
2010
ACM
Software artifacts usually have static program constraints and these constraints should be satisfied in each reuse. In addition to this, the developers are also required to satisf...
90
Voted
DAC
2006
ACM
15 years 3 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
FASE
2009
Springer
15 years 1 months ago
2009
Springer
Model checking tools based on the iterative refinement of predicate abstraction (e.g., Slam and Blast) often feature a specification language for expressing complex behavior rules....