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» Verification of Model Transformations
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DAC
2007
ACM
15 years 9 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
ICCAD
2010
IEEE
186views Hardware» more  ICCAD 2010»
15 years 3 months ago
Efficient state space exploration: Interleaving stateless and state-based model checking
State-based model checking methods comprise computing and storing reachable states, while stateless model checking methods directly reason about reachable paths using decision proc...
Malay K. Ganai, Chao Wang, Weihong Li
EMSOFT
2008
Springer
15 years 6 months ago
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
Aimed at verifying safety properties and improving simulation coverage for hybrid systems models of embedded control software, we propose a technique that combines numerical simul...
Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shash...
IJIT
2004
15 years 6 months ago
Modeling Biology Inspired Reactive Agents Using X-machines
Recent advances in both the testing and verification of software based on formal specifications of the system to be built have reached a point where the ideas can be applied in a p...
George Eleftherakis, Petros Kefalas, Anna Sotiriad...
FMSD
2006
140views more  FMSD 2006»
15 years 5 months ago
Dealing with practical limitations of distributed timed model checking for timed automata
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
Víctor A. Braberman, Alfredo Olivero, Ferna...