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JISE
1998
106views more  JISE 1998»
14 years 9 months ago
Control / Data-Flow Analysis for VHDL Semantic Extraction
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified....
Yee-Wing Hsieh, Steven P. Levitan
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
15 years 1 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
DAC
2005
ACM
14 years 11 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
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POPL
2005
ACM
15 years 10 months ago
Automated soundness proofs for dataflow analyses and transformations via local rules
We present Rhodium, a new language for writing compiler optimizations that can be automatically proved sound. Unlike our previous work on Cobalt, Rhodium expresses optimizations u...
Sorin Lerner, Todd D. Millstein, Erika Rice, Craig...
SPE
2002
154views more  SPE 2002»
14 years 9 months ago
Bytecode verification on Java smart cards
This article presents a novel approach to the problem of bytecode verification for Java Card applets. By relying on prior off-card bytecode transformations, we simplify the byteco...
Xavier Leroy