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VLSID
2002
IEEE
83views VLSI» more  VLSID 2002»
15 years 10 months ago
Identifying Redundant Wire Replacements for Synthesis and Verification
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
Katarzyna Radecka, Zeljko Zilic
APN
1997
Springer
15 years 1 months ago
Verification of Workflow Nets
Abstract. Workflow management systems will change the architecture of future information systems dramatically. The explicit representation of business procedures is one of the main...
Wil M. P. van der Aalst
SAC
2008
ACM
14 years 9 months ago
A framework for performance evaluation and functional verification in stochastic process algebras
Despite its relatively short history, a wealth of formalisms exist for algebraic specification of stochastic systems. The goal of this paper is to give such formalisms a unifying ...
Hossein Hojjat, Mohammad Reza Mousavi, Marjan Sirj...
AEI
1999
60views more  AEI 1999»
14 years 9 months ago
Rule-base content verification using a digraph-based modelling approach
Ensuring that the content of a rule-base, which is being encoded, is free from problems of consistency, completeness, and conciseness, is necessary to avoid any performance errors...
G. S. Gursaran, S. Kanungo, A. K. Sinha
DAC
2005
ACM
15 years 10 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin