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» Verification of System Level Model Transformations
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EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
BPM
2006
Springer
126views Business» more  BPM 2006»
14 years 11 months ago
Verification of Business Process Integration Options
Abstract. We propose a meta-meta framework architecture for supporting the behaviour based integration of two business processes. The meta-meta level provides basic integration ope...
Georg Grossmann, Michael Schrefl, Markus Stumptner
FMAM
2010
157views Formal Methods» more  FMAM 2010»
14 years 7 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
15 years 3 months ago
On the verification of automotive protocols
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pa...
DAC
2006
ACM
15 years 3 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra