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» Verification of System Level Model Transformations
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ENTCS
2008
106views more  ENTCS 2008»
14 years 9 months ago
Towards Verifying Model Transformations
In model-based software development, a complete design and analysis process involves designing the system using the design language, converting it into the analysis language, and ...
Anantha Narayanan, Gabor Karsai
MEMOCODE
2010
IEEE
14 years 7 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
82
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FMCAD
2007
Springer
15 years 1 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
SWQD
2012
234views more  SWQD 2012»
13 years 5 months ago
BIM: A Methodology to Transform Business Processes into Software Systems
This manuscript proposes a guiding methodology to obtain a software system that supports the execution of the business processes existing within an organization. The methodology pr...
Francisco J. Duarte, Ricardo Jorge Machado, Jo&ati...
85
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AHS
2007
IEEE
251views Hardware» more  AHS 2007»
15 years 1 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan