1399 search results - page 31 / 280 » Verification of Test Suites |
112
Voted
ASWEC
2007
IEEE
15 years 5 months ago
2007
IEEE
Testers often represent systems under test in input parameter models. These contain parameters with associated values. Combinations of parameter values, with one value for each pa...
115
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COMPSAC
2007
IEEE
15 years 5 months ago
2007
IEEE
Despite the availability of a variety of program analysis tools, evaluation of these tools is difficult, as only few benchmark suites exist. Existing benchmark suites lack the uni...
158
Voted
GLVLSI
2009
IEEE
14 years 11 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
126
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GLVLSI
2007
IEEE
15 years 5 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
102
Voted
SE
2007
15 years 3 months ago
2007
: This paper is a tutorial on the principles and applications of static tion by Abstract Interpretation to development, verification and validation ded applications. The topics cov...