304 search results - page 13 / 61 » Verification of Timed Systems Using POSETs |
73
Voted
ISARCS
2010
14 years 11 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
FORMATS
2007
Springer
15 years 1 months ago
2007
Springer
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
90
Voted
SIGSOFT
2007
ACM
15 years 10 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
91
Voted
FORMATS
2009
Springer
15 years 1 months ago
2009
Springer
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...