308 search results - page 30 / 62 » Verification of object-oriented simulation designs |
FDL
2007
IEEE
15 years 4 months ago
2007
IEEE
—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generate...
74
Voted
ECRTS
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
FPL
1999
Springer
15 years 1 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
79
Voted
MICRO
1999
IEEE
15 years 1 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...