29 search results - page 3 / 6 » Verification of timed circuits with symbolic delays |
81
Voted
VLSID
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
ICCAD
2003
IEEE
15 years 2 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
TCAD
1998
14 years 9 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
ASYNC
1997
IEEE
15 years 1 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...