29 search results - page 4 / 6 » Verification of timed circuits with symbolic delays |
103
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
ICCAD
2003
IEEE
15 years 2 months ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
110
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TCAD
2008
14 years 9 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
IPPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Enabling circuit switching in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. However, in ...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...