196 search results - page 10 / 40 » Verification of timing Properties of VHDL |
112
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SPIN
2000
Springer
15 years 3 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
89
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DAC
1999
ACM
15 years 4 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
129
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FTRTFT
1992
Springer
15 years 3 months ago
1992
Springer
Real-Time Logic is a formal notation for reasoning about temporal behaviour. Z is a general purpose specification language, but lacks explicit features for expressing real-time co...
HYBRID
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
112
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EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...