196 search results - page 21 / 40 » Verification of timing Properties of VHDL |
CAV
2001
Springer
15 years 3 months ago
2001
Springer
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
100
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FMCAD
2008
Springer
15 years 1 months ago
2008
Springer
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...
117
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FORMATS
2007
Springer
15 years 3 months ago
2007
Springer
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
100
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BPM
2007
Springer
15 years 3 months ago
2007
Springer
The collaborative business process can be unreliable when business partners collaborate in a peer-to-peer fashion without central control. Therefore, an important issue that needs ...