584 search results - page 5 / 117 » Verification-Aware Microprocessor Design |
COMPUTER
1998
14 years 11 months ago
1998
JSA
2008
14 years 10 months ago
2008
106
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TCAD
2002
14 years 11 months ago
2002
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
JILP
2002
14 years 11 months ago
2002
As microprocessor designs continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models...
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...