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ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
15 years 3 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
CODES
2001
IEEE
15 years 3 months ago
The TACO protocol processor simulation environment
Network hardware design is becoming increasingly challenging because more and more demands are put on network bandwidth and throughput requirements, and on the speed with which ne...
Seppo Virtanen, Johan Lilius
ICONS
2008
IEEE
15 years 6 months ago
Analysis of Hybrid Systems Using HySAT
In this paper we describe the complete workflow of analyzing the dynamic behavior of safety-critical embedded systems with HySAT. HySAT is an arithmetic constraint solver with a ...
Christian Herde, Andreas Eggers, Martin Fränz...
FPL
2008
Springer
91views Hardware» more  FPL 2008»
15 years 1 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
80
Voted
SC
2005
ACM
15 years 5 months ago
A Power-Aware Run-Time System for High-Performance Computing
For decades, the high-performance computing (HPC) community has focused on performance, where performance is defined as speed. To achieve better performance per compute node, mic...
Chung-Hsing Hsu, Wu-chun Feng