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FMOODS
2007
15 years 2 months ago
Verifying Distributed, Event-Based Middleware Applications Using Domain-Specific Software Model Checking
The success of distributed event-based infrastructures such as SIENA and Elvin is partially due to their ease of use. Even novice users of these infrastructures not versed in distr...
L. Ruhai Cai, Jeremy S. Bradbury, Jürgen Ding...
ITC
2003
IEEE
113views Hardware» more  ITC 2003»
15 years 5 months ago
Fault Injection for Verifying Testability at the VHDL Level
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
S. R. Seward, Parag K. Lala
96
Voted
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 4 months ago
Towards verifying VHDL descriptions of processors
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
Laurent Arditi, Hélène Collavizza
JISBD
2001
15 years 1 months ago
Verifying Reuse Contracts with a Component Model
The Itacio component model intends to bring a method of verifying software systems made up of ts. This method can be applied at different levels of abstraction, and to different f...
Agustín Cernuda del Río, José...
SAS
2009
Springer
281views Formal Methods» more  SAS 2009»
16 years 1 months ago
A Verifiable, Control Flow Aware Constraint Analyzer for Bounds Check Elimination
The Java programming language requires that out-of-bounds array accesses produce runtime exceptions. In general, this requires a dynamic bounds check each time an array element is...
David Niedzielski, Jeffery von Ronne, Andreas Gamp...