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» Verifying Progress in Timed Systems
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ISOLA
2010
Springer
14 years 10 months ago
An Interface Algebra for Estimating Worst-Case Traversal Times in Component Networks
Abstract. Interface-based design relies on the idea that different components of a system may be developed independently and a system designer can connect them together only if th...
Nikolay Stoimenov, Samarjit Chakraborty, Lothar Th...
ISORC
2005
IEEE
15 years 5 months ago
Model-Checking of Component-Based Event-Driven Real-Time Embedded Software
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
Zonghua Gu, Kang G. Shin
IEEEARES
2008
IEEE
15 years 6 months ago
RTQG: Real-Time Quorum-based Gossip Protocol for Unreliable Networks
We consider scheduling real-time tasks in the presence of message loss and Byzantine node failures in unreliable networks. We present scheduling algorithms called RTQG and RTQG-B....
Bo Zhang, Kai Han, Binoy Ravindran, E. Douglas Jen...
IASTEDSE
2004
15 years 1 months ago
A coordination architecture for time-dependent components
The integration of distributed, data dependent components requires a data synchronisation model. We consider a class of systems where data-dependent components produce data in dis...
Michael N. Barth, Alexander Knapp
RTSS
2007
IEEE
15 years 6 months ago
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...
Marko Bertogna, Michele Cirinei