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» Verifying Safety Properties with the TLA Proof System
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119
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SAC
2010
ACM
14 years 10 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
LICS
2012
IEEE
13 years 3 months ago
Logics of Dynamical Systems
—We study the logic of dynamical systems, that is, logics and proof principles for properties of dynamical systems. Dynamical systems are mathematical models describing how the s...
André Platzer
126
Voted
CODES
2008
IEEE
15 years 2 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
ICST
2009
IEEE
14 years 10 months ago
Euclide: A Constraint-Based Testing Framework for Critical C Programs
Euclide is a new Constraint-Based Testing tool for verifying safety-critical C programs. By using a mixture of symbolic and numerical analyses (namely static single assignment for...
Arnaud Gotlieb
142
Voted
CADE
2008
Springer
16 years 29 days ago
Exploring Model-Based Development for the Verification of Real-Time Java Code
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
Niusha Hakimipour, Paul A. Strooper, Roger Duke