Sciweavers

1093 search results - page 102 / 219
» Verifying VLSI Circuits
Sort
View
ISVLSI
2006
IEEE
95views VLSI» more  ISVLSI 2006»
15 years 3 months ago
PLAs in Quantum-dot Cellular Automata
Abstract— Research in the fields of physics, chemistry and electronics has demonstrated that Quantum-dot Cellular Automata (QCA) is a viable alternative for nano-scale computing...
Xiaobo Sharon Hu, Michael Crocker, Michael T. Niem...
SBCCI
2005
ACM
132views VLSI» more  SBCCI 2005»
15 years 3 months ago
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
Leonardo Barboni, Rafaella Fiorelli
DAC
2007
ACM
15 years 1 months ago
CAD Implications of New Interconnect Technologies
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
Louis Scheffer
IOLTS
2009
IEEE
174views Hardware» more  IOLTS 2009»
15 years 4 months ago
ATPG-based grading of strong fault-secureness
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...
Marc Hunger, Sybille Hellebrand, Alejandro Czutro,...
FMSD
2010
123views more  FMSD 2010»
14 years 8 months ago
Analog property checkers: a DDR2 case study
Abstract Modeling and Simulation Aided Verification of Analog/MixedSignal Circuits S. Little and C. Myers (University of Utah, USA) Monday, July 14, 14:00-17:00 4 14:00-14:40 fSpic...
Kevin D. Jones, Victor Konrad, Dejan Nickovic