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» Verifying VLSI Circuits
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VLSID
2005
IEEE
126views VLSI» more  VLSID 2005»
15 years 10 months ago
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
Jaijeet S. Roychowdhury
VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
15 years 10 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
15 years 10 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
VLSID
2003
IEEE
82views VLSI» more  VLSID 2003»
15 years 10 months ago
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
We propose a non-intrusive methodology for concurrent fault detection in FSMs. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor ...
Petros Drineas, Yiorgos Makris
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
15 years 10 months ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri