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» Verifying VLSI Circuits
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ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
15 years 4 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar
ENGL
2007
180views more  ENGL 2007»
14 years 11 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
K. Paramasivam, K. Gunavathi
DAC
1995
ACM
15 years 3 months ago
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits
Abstract We observe that the switching activity at a circuit node, also called the transition density, can be extremely sensitive to the circuit internal delays. As a result, sligh...
Farid N. Najm, Michael Y. Zhang
DAC
1995
ACM
15 years 3 months ago
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits
With the advent of portable and high-density microelectronic devices, the power dissipation of integrated circuits has become a critical concern. Accurate and e cient power estimat...
Farid N. Najm
ICCAD
2000
IEEE
73views Hardware» more  ICCAD 2000»
15 years 4 months ago
Simulation and Optimization of the Power Distribution Network in VLSI Circuits
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj