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» Verifying VLSI Circuits
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ARVLSI
2001
IEEE
258views VLSI» more  ARVLSI 2001»
15 years 1 months ago
Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits
We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFET's in their subthreshold region as well as c...
Vincent F. Koosh, Rodney M. Goodman
71
Voted
NIPS
2004
14 years 11 months ago
Sub-Microwatt Analog VLSI Support Vector Machine for Pattern Classification and Sequence Estimation
An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an...
Shantanu Chakrabartty, Gert Cauwenberghs
68
Voted
DAC
1999
ACM
15 years 10 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
FMCAD
2008
Springer
14 years 11 months ago
Verifying an Arbiter Circuit
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...
Chao Yan, Mark R. Greenstreet
EMSOFT
2004
Springer
15 years 1 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha