1093 search results - page 85 / 219 » Verifying VLSI Circuits |
113
click to vote
ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
— The rapid control of sonar-guided vehicles through obstacle fields has been a goal of robotics for decades. How sensory data is represented strongly affects how obstacles and g...
108
Voted
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
157
Voted
DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
147
Voted
GLVLSI
2000
IEEE
15 years 8 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
136
click to vote
VLSID
1999
IEEE
15 years 8 months ago
1999
IEEE
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...