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» Verifying and Validating Simulation Models
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ICC
2007
IEEE
135views Communications» more  ICC 2007»
15 years 4 months ago
New Results on Single-Step Power Control System in Finite State Markov Channel: Power Control Error Modelling and Queueing Varia
— The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is h...
Shi-Yong Lee, Min-Kuan Chang
AAAI
1990
14 years 11 months ago
Approximation Reformulations
Although computers are widely used to simulate complex physical systems, crafting the underlying models that enable computer analysis remains difficult. When a model is created fo...
Daniel S. Weld
ISQED
2003
IEEE
119views Hardware» more  ISQED 2003»
15 years 3 months ago
System and Framework for QA of Process Design Kits
In this paper, we evaluate the dependencies between tools, data and environment in process design kits, and present a framework for systematically analyzing the quality of the des...
M. C. Scott, M. O. Peralta, Jo Dale Carothers
FMCAD
2004
Springer
15 years 1 months ago
A Simple Method for Parameterized Verification of Cache Coherence Protocols
Abstract. We present a simple method for verifying the safety properties of cache coherence protocols with arbitrarily many nodes. Our presentation begins with two examples. The fi...
Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon P...
FMSD
2010
123views more  FMSD 2010»
14 years 8 months ago
Analog property checkers: a DDR2 case study
Abstract Modeling and Simulation Aided Verification of Analog/MixedSignal Circuits S. Little and C. Myers (University of Utah, USA) Monday, July 14, 14:00-17:00 4 14:00-14:40 fSpic...
Kevin D. Jones, Victor Konrad, Dejan Nickovic