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» Verifying and Validating Simulation Models
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HPCA
2006
IEEE
15 years 10 months ago
Completely verifying memory consistency of test program executions
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
Chaiyasit Manovit, Sudheendra Hangal
ICSE
2012
IEEE-ACM
13 years 1 days ago
Engineering and verifying requirements for programmable self-assembling nanomachines
—We propose an extension of van Lamsweerde’s goal-oriented requirements engineering to the domain of programmable DNA nanotechnology. This is a domain in which individual devic...
Robyn R. Lutz, Jack H. Lutz, James I. Lathrop, Tit...
73
Voted
WSC
2001
14 years 11 months ago
Production scheduling validity in high level supply chain models
Although they focus on the big picture, high level supply chain models cannot gloss over the capacity of production nodes to meet production allocations. Capacity is not simply a ...
David J. Parsons, Richard A. Phelps
SPIN
2004
Springer
15 years 3 months ago
Validation of UML Models via a Mapping to Communicating Extended Timed Automata
Abstract. We present a technique and a tool for model-checking operational UML models based on a mapping of object oriented UML models into a framework of communicating extended ti...
Iulian Ober, Susanne Graf, Ileana Ober
70
Voted
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
15 years 4 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng