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» Verifying and validating a simulation model
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EMSOFT
2010
Springer
14 years 7 months ago
PinaVM: a systemC front-end based on an executable intermediate representation
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
Kevin Marquet, Matthieu Moy
77
Voted
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 3 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski
ICCS
2005
Springer
15 years 3 months ago
GIVS: Integrity Validation for Grid Security
Abstract. In this paper we address the problem of granting the correctness of Grid computations. We introduce a Grid Integrity Validation Scheme (GIVS) that may reveal the presence...
Giuliano Casale, Stefano Zanero
BMAS
2000
IEEE
15 years 2 months ago
VHDL Based Simulation of a Sigma-Delta A/D Converter
The VHDL based mixed-signal event-driven (MixED) simulation method is employed to simulate a sigma-delta modulator for A/D conversion. Results are verified by experimental data an...
Martin Schubert
ISORC
1999
IEEE
15 years 1 months ago
Applying Use Cases for the Requirements Validation of Component-Based Real-Time Software
Component-based software development is a promising way to improve quality, time to market and handle the increasing complexity of software for real-time systems. In this paper th...
Wolfgang Fleisch