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» Verifying and validating a simulation model
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IMCSIT
2010
14 years 7 months ago
Software and hardware in the loop component for an IEC 61850 Co-Simulation platform
The deployment of IEC61850 standard in the world of substation automation system brings to the use of specific strategies for architecture testing. To validate IEC61850 architectur...
Haffar Mohamad, Thiriet Jean Marc
GECCO
2005
Springer
103views Optimization» more  GECCO 2005»
15 years 3 months ago
Validation of evolutionary activity metrics for long-term evolutionary dynamics
As artificial life systems grow in number and sophistication, it is becoming increasingly important that the field agree on principled metrics for evaluating them. This report d...
Andrew Stout, Lee Spector
TVLSI
2008
140views more  TVLSI 2008»
14 years 9 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
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WSC
2007
15 years 15 hour ago
Automatic generation of simulation models for semiconductor manufacturing
This article gives an overview of a framework for automatically generating large-scale simulation models from a domain specific problem definition data schema, here semiconductor ...
Ralph Mueller, Christos Alexopoulos, Leon F. McGin...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
15 years 1 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham