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» Versatile Imaging Architecture Based on a System on Chip
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IJCNN
2000
IEEE
15 years 4 months ago
A 2D Neuromorphic VLSI Architecture for Modeling Selective Attention
Selectiveattentionis a mechanismsused to sequentiallyselectthe spatiallocationsof salientregionsin the sensor’sfieldof view. This mechanism overcomesthe problem of flooding limi...
Giacomo Indiveri
SDL
2003
147views Hardware» more  SDL 2003»
15 years 1 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 5 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
CSREAESA
2006
15 years 1 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
DAC
2001
ACM
16 years 18 days ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...