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» Versatile Imaging Architecture Based on a System on Chip
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ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 3 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
ICDAR
2005
IEEE
15 years 5 months ago
Text Recognition of Low-resolution Document Images
Cheap and versatile cameras make it possible to easily and quickly capture a wide variety of documents. However, low resolution cameras present a challenge to OCR because it is vi...
Charles E. Jacobs, Patrice Y. Simard, Paul A. Viol...
ICIP
2003
IEEE
16 years 1 months ago
Embedded co-processor architecture for CMOS based image acquisition
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
Julien Dubois, Marco Mattavelli
KES
1998
Springer
15 years 3 months ago
Insect vision based motion detection
The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are des...
X. T. Nguyen
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 5 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...