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» Versatile Imaging Architecture Based on a System on Chip
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CODES
2002
IEEE
15 years 4 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
60
Voted
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
15 years 1 months ago
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioann...
101
Voted
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 5 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
VLSID
2000
IEEE
164views VLSI» more  VLSID 2000»
15 years 4 months ago
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kum...
CIT
2004
Springer
15 years 5 months ago
FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder
Abstract. Both encryption and digital watermarking techniques need to be incorporated in a digital rights management framework to address different aspects of content management. W...
Saraju P. Mohanty, Renuka Kumara C., Sridhara Naya...