487 search results - page 32 / 98 » Versatile Imaging Architecture Based on a System on Chip |
VLSID
2000
IEEE
15 years 4 months ago
2000
IEEE
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
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GLVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
ISNN
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
FDL
2003
IEEE
15 years 5 months ago
2003
IEEE
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...